Strides in CPU design

So far, we have made significant strides on our CPU project. I have completed the 8-bit adder circuit. It definitely isn’t the hardest board we will make, but it was still complex in terms of layout and the sheer amount of traces.

As you can see here, the base addition is handled by the bottom-ranked XOR gates, which handle if 0s are added together or a 0 and a 1 are added together. The top-ranked AND gates allow for the carry (1+1). The XOR gates on the very right are the ones that recombine the base sum with the carry sum to get the final 9-bit sum. It is 9-bit because you get the 8-bit sum plus a carry, which is used as a flag to tell the CPU to throw an overflow exception.

Because we decided to offload signal conditioning entirely to a separate daughterboard, this PCB contains only logic ICs and connectors, with no local resistors, capacitors, or other electrical mediators. That simplification made routing cleaner and the design more modular.